Logical Effort

 Logical Effort delay calculation a) Calculate the minimum path effort between CLK and CLKBAR. b) Choose the relative transistor sizes to achieve this delay. c) Calculate the actual delay (in specs) between CLK and CLKBAR. Assume minimum transistor size to be W=1um L=0.18um (so the inverter with 30C has an NMOS with W=10um L=0.18um, and PMOS with W=20um L=0.18um). And assume RN=2kW/um, RP=4kW/um, CgN=CdN=CgP=CgN= 2fF/um (all assuming L=0.18um) d) Assume that the clock period is 8x the delay from CLK to CLKBAR. What is the Minimum CLK period (in spec’s or niece’s)? What is the Maximum CLK frequency (1/CLK period – in Hz).  For more information on Logical Effort read this: https://en.wikipedia.org/wiki/Logical_effort

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